In such a known stored program controlled system, e.g., as described in U.S. Pat. No. 4,053,947, the address and control information is read from an instruction memory. The known information bus includes a data bus and an order bus for transferring control information to interface means of the function units. The known addressing means includes an address bus for transferring the address to all the function units of the system and includes address decoders, each of which is arranged in its interface means. Each of the address decoders generates an access signal only if the address bus transfers the address number associated with its function unit. The access signal is used to control an input gate arranged in this function unit, this gate being connected to the information bus such that in an activation state it feeds its function unit with the intended control information.
Relatively easily remedied system errors occur if a correctly addressed function unit receives incorrect control information, thus executing an incorrect function. In this case the remaining function units of the system will be unaffected. However, if the addressing process is executed incorrectly, a serious operational error occurs. The intended function unit, which has then not received an access signal, does not carry out the intended function, but some other unidentified function unit will be disturbed in its ordinary functional performance. To achieve greater security against the unintentional selection of a function unit, it is already known, e.g., from the U.S. Pat. Nos. 3,868,641 and 4,165,533, to provide each of the function units with duplicated address decoders.